Method of operating a buffer memory to provide a trigger pattern by storing a trigger code in preselected areas of the buffer memory

ABSTRACT

Selected memory locations of a buffer memory having an m x n address space are loaded each with a trigger code. First and second data words, in bits and n bits respectively, are used to read the numerical value stored at a memory location of the buffer memory. If the numerical value bears a predetermined relationship to the trigger code, a predetermined response signal is generated.

BACKGROUND OF THE INVENTION

This invention relates to a method of operating a buffer memory toprovide a trigger pattern.

A buffer memory is a random access memory having memory locations thatmap to map to displayable pixels of an imaging device. For example, abuffer memory may be used to store a virtual image of a display that isto be provided on a cathode ray tube (CRT) display device of arasterscan oscilloscope. In this case, the pixels of the imaging deviceare addressed in accordance with a raster-scan pattern and the contentsof the buffer memory are used to determine the intensity with which eachpixel of the display device is illuminated.

An oscilloscope is conventionally used to display a waveformrepresentative of change of a first variable as a function of a secondvariable. It will be convenient in the following description to assumefrom time to time that the first variable is the magnitude of a measuredquantity and that the second variable is time, so that the waveformrepresents magnitude of the measured quantity as a function of time, butit will be understood that the second variable need not be time or evenrelated to time. In a known rasterscan oscilloscope, waveform datacomposed of a stream of pairs of related data words is acquired. Oneword of each pair represents the value of a first variable and the otherword of the pair represents the value of a second variable. Typically,the first variable is the magnitude of a sample of a signal existing ata test point and the second variable is the time at which the sample wastaken. The range of values of the first variable is transformed so thatit is the same as the range of the address space of the oscilloscope'sdisplay device along the vertical deflection axis, and the range ofvalues of the second variable is transformed so that it is the same asthe range of the address space of the display device along thehorizontal deflection axis. Each pair of related data words in thewaveform data then defines a discrete location in the address space ofthe display device. For each such pair, the content of the correspondingmemory location of the buffer memory is read, incremented and writtenback to the same memory location. A display of the contents of thebuffer memory illustrates graphically the function that relates thefirst variable to the second variable, and the relative intensities ofthe pixels represents the relative frequencies of occurrence of thevarious events defined by the pairs of related digital words.

U.S. Pat. No. 4,510,571 (Dagostino et al) discloses a vector digitaloscilloscope having an acquisition waveform memory into which samplevalues are loaded in linear fashion and a reference waveform memory inwhich sample values representing a reference waveform are stored. Thewaveform record stored in the acquisition waveform memory is comparedwith the waveform record stored in the reference waveform memory, andwhen a deviation from the reference waveform, beyond a predeterminedtolerance, is detected in a newly acquired waveform, a record of the newwaveform is stored in a changed waveform memory.

It is known to test waveform data representing signal magnitude as afunction of time to determine whether the signal magnitude falls withinan envelope by storing pairs of minimum and maximum values associatedwith the sample times respectively. When a new sample value is acquired,it is compared with the maximum and minimum values for the sample time.Typically, if the new sample value is not between the minimum andmaximum values, a trigger is generated to initiate termination of thesignal acquisition.

This type of envelope testing is subject to disadvantage since it islimited to a single pair of minimum and maximum values for each sampletime and therefore is applicable only to single-valued waveforms. It isnecessary to perform memory access operations to read the minimum andmaximum values and carry out the comparison.

A generalization of envelope testing is accomplished by definingpolygons in a display space and converting each polygon into an envelopeof min-max pairs. As each sample value is processed, it is compared toan envelope data base. If the data point is within the X-extent of anenvelope, and is between the minimum and maximum values of Y for that Xpoint of the envelope, a trigger is generated. This envelope testingprocedure requires several steps to determine if a single data pointjustifies a trigger.

SUMMARY OF THE INVENTION

In accordance with a first aspect of the present invention, a method ofoperating a buffer memory that comprises an array of memory locationsdefined by an n-bit address word and an m-bit address word, each memorylocation being capable of storing a numerical value composed of at leasttwo bits, comprises the steps of loading selected memory locations ofthe buffer memory each with a trigger code, receiving a first data wordof n-bits and a second data word of m-bits, reading from the buffermemory the numerical value stored at the memory location whose addressis defined by the first and second data words, and if the numericalvalue read in the preceding step bears a predetermined relationship tosaid trigger code, generating a predetermined response signal.

In accordance with a second aspect of the invention, a method ofoperating a buffer memory that comprises a multiplicity of memorylocations in an address space having a first dimension and a seconddimension, each memory location being capable of storing a numericalvalue composed of at least two bits, comprises the steps of:

(a) loading the memory locations within a selected area of the addressspace each with a trigger code,

(b) acquiring a succession of pairs of data words each composed of afirst data word and a second data word, the range of the first data wordbeing equal to at least the range of the first dimension of the addressspace and the range of the second data word being equal to at least therange of the second dimension of the address space,

(c) for each pair of data words,

(i) reading from the buffer memory the numerical value stored at thememory location whose address in the first dimension of the addressspace is defined by an address word related in a predetermined fashionto the first data word and whose address in the second dimension of theaddress space is defined by an address word related in a predeterminedfashion to the second data word,

(ii) comparing said numerical value with said trigger code, and

(iii) if said numerical value bears a predetermined relationship to saidtrigger code, generating a predetermined response signal, and

(iv) otherwise incrementing said numerical value by a predeterminedamount and writing the incremented numerical value to the memorylocation that was read in step (c) (i),

(d) subsequently generating pairs of first and second address words, and

(e) for each pair of address words

(i) reading from the buffer memory the numerical value stored at thememory location defined by the first and second address words, and

(ii) if said numerical value bears a predetermined relationship to saidtrigger code, writing the numerical value unchanged back to the memorylocation read in step (e) (i), and

(iii) otherwise decrementing the numerical value by a selected amountand writing the decremented numerical value back to the memory locationread in step (e) (i).

In accordance with a third aspect of the invention, buffer memoryapparatus comprises a multiplicity of memory locations occupying atwo-dimensional address space and each capable of storing a numericalvalue composed of at least two bits, means for defining an area of theaddress space and loading the memory locations within the defined areaeach with a trigger code, input means for receiving a succession ofpairs of data words each composed of a first data word and a second dataword, means responsive to a pair of data words received by the inputmeans to read from the buffer memory the numerical value stored at thememory location whose address is defined by a first address word relatedin a predetermined fashion to the first data word and a second addressword related in a predetermined fashion to the second data word, comparethe numerical value read from the buffer memory with said trigger code,and if said numerical value bears a predetermined relationship to saidtrigger code, generate a predetermined response signal.

BRIEF DESCRIPTION OF THE DRAWING

For a better understanding of the invention, and to show how the samemay be carried into effect, reference will now be made, by way ofexample, to the accompanying drawing the single FIGURE of which is aschematic diagram of a raster-scan digital oscilloscope embodying thepresent invention.

In order to avoid cluttering the drawing, components that are nothelpful in understanding the invention have not been illustrated.

DETAILED DESCRIPTION

The illustrated oscilloscope 2 comprises a CRT display device 4 having adisplay screen 6 and a deflection circuit 8. Oscilloscope 2 operatesunder control of a precessor 18, which causes the oscilloscope toexecute various operations. Processor 18 communicates with othercomponents of the oscilloscope over a system bus 22. An operator of theoscilloscope is able to adjust various settings of the oscilloscopethrough an operator interface 20. Oscilloscope 2 also comprises a videocontroller 14 that operates in response to a pixel clock signal PCgenerated by a pixel clock generator 16 and generates horizontal andvertical sync pulses H and V. Video controller 16 also generates a frameend signal FE synchronously with the vertical sync pulse V.

The sync pulses are applied to deflection circuit 8, which generateshorizontal and vertical deflection signals that cause the electron beamof the CRT to be deflected over the screen of the CRT in a horizontalraster pattern composed of 512 lines. During each horizontal line time,512 pixel clock pulses are generated. In this manner, the display screenis divided into 262,144 pixels.

Oscilloscope 2 also comprises a dual-ported buffer memory 36 having262,144 addressable memory locations. Memory 36 is composed of foursegments 36₀, 36₁, 36₂ and 36₃ each organized as 512 rows containing 128locations, and each memory location is able to store a four-bitnumerical value. Memory 36 has a parallel port connected to a data bus44 and a serial port connected to a video digital-to-analog converter(V-DAC) 42.

At the beginning of each horizontal scanline retrace, video controller14 initiates a display refresh cycle. During this cycle, the videocontroller applies a HOLD signal to a memory address generator 60 and toan address bus arbitrator 64. Arbitrator 64 controls the state of anaddress bus multiplexer 66, which has one state in which it selectsvideo controller 14 and another state in which it selects memory addressgenerator 60. Memory address generator 60 acknowledges the HOLD signalby issuing a HOLDACK signal to bus arbitrator 64. Arbitrator 64 respondsto the HOLD and HOLDACK signals by placing multiplexer 66 in the statein which it selects video controller 14. Video controller 14 places anine-bit row address, corresponding to the next scanline to bedisplayed, on address bus 24. In this fashion, one row of memorylocations in each segment of memory 36 is selected. The contents of the128 memory locations in the selected row of each segment are shifted toan internal shift register of the memory segment. Memory segments 36₀,36₁, 36₂ and 36₃ are selected in repetitive sequence in response tosuccessive pixel clock pulses during the active interval of thehorizontal scanline, and as each segment is selected the contents of itsinternal shift register are shifted out through the serial port. Thus,the values shifted through the serial port are in the sequence 36₀, 36₁,36₂, 36₃, 36₀, 36₁ and so on, and are synchronized with deflection ofthe electron beam under control of the deflection signals generated bydeflection circuit 8. The sequence of numerical values read out frommemory 36 is converted into an analog intensity signal by V-DAC 42. Theintensity signal is used to control the intensities with which thepixels on one line of the raster are illuminated. Thus, the addressablememory locations of buffer memory 36 map on a one-to-one basis todisplayable pixels on CRT screen 6 and are scanned synchronously withthe scanning of display screen 6 by the electron beam of display device4. The intensity with which a given pixel is illuminated in the displayrefresh cycle depends on the numerical value stored in the correspondingmemory location. Since the numerical values stored in buffer memory 36each have four bits, display device 4 is able to display 16 intensitylevels (off and 15 gray levels).

Oscilloscope 2 comprises an acquisition circuit 54 that provideswaveform data, comprising pairs of digital words. One word of each pairrepresents the value of a first parameter and the other word of the pairrepresents the value of a second parameter. The waveform data pairs areapplied to a memory address generator 60. In response to each waveformdata pair, and scale and offset signals received from operator interface20, memory address generator 60 generates a nine-bit Y address word anda nine-bit X address word. If video controller 14 requires access to bus24, memory address generator 60 temporarily stores the X and Y addresswords. When video controller 14 no longer requires access to bus 24, forexample during the vertical retrace interval, arbitrator 64 placesmultiplexer 66 in the state in which it selects memory address generator60, and memory address generator 60 applies the Y address word and theupper seven bits of the X address word to multiplexed address bus 24 asa 16-bit memory address vector. Address bus 24 is eight bits wide, andtherefore the memory address vector is supplied in two words of eightbits each, one word being composed of the upper eight bits of the Yaddress and the other of the X address and the LSB of the Y address.Memory address generator 60 applies the two LSBs of the X address wordto a decoder 62, which decodes the two LSBs of the X address word intoone of four binary values.

Before carrying out a signal acquisition, the operator defines a triggerregion in the address space of display device 4. The trigger region mayconstitute one or more closed figures, in which case the trigger regionmay be defined by using the operator interface to move the cursor of theoscilloscope around the boundary of each closed figure. Processor 18,acting through buses 22 and 44, loads a trigger code into the memorylocations corresponding to the pixels touched by the cursor whendefining the boundary. For each value of Y in the address space of thedisplay device at which two pixels are touched by the cursor, processor18 also loads the trigger code into all memory locations correspondingto the pixels between those two touched pixels. Alternatively, thetrigger region may be the region outside a closed figure, in which casethe locations corresponding to the pixels that are inside the boundaryof the closed figure can be identified in the manner described above andthe trigger code can be loaded into all memory locations correspondingto the pixels other than those inside the boundary. Processor 18 alsoloads the trigger code into a register 84. It will be understood thatsince memory 36 is in four segments, in general the trigger region ofthe display address space will correspond to four trigger regions in theaddress spaces of the memory segments respectively.

During a signal acquisition, buffer memory 36 operates in a read,modify, write mode. The numerical values stored at the four memorylocations, identified by a memory address vector applied to bus 24 bymemory address generator 60, are read from the buffer memory and areplaced on the data bus 44. A pixel manipulator 70 reads the numericalvalues from the data bus and loads them into a latch 72. Latch 72applies the numerical values read from bus 44 to the address lines of alook-up RAM 74 whose data lines are connected to one input of amultiplexer 78. Look-up RAM 74 returns four output values, related tothe four input values respectively by a look-up table stored in RAM 74,and these modified values are placed on the data bus by multiplexer 78.On the basis of the two LSBs of the X address word generated by memoryaddress generator 60, decoder 62 applies a write enable signal to one ofthe four segments of memory 36, and the appropriate one of the fourmodified values is written back into the appropriate segment of thebuffer memory 36. The contents of the corresponding memory locations inthe other three segments of memory 36 remain unchanged.

During the acquisition, the values read from buffer memory 36 are alsoapplied to a comparator 82, which compares each value with the triggercode stored in register 84. If one of the values read from buffer memory36 is equal to the trigger code, the corresponding output of thecomparator is logical one, otherwise it is logical zero. The "equal to"outputs of comparator 82 are connected to a multiplexer 86, whichreceives at its control input the two LSBs of the X address wordgenerated by memory address generator 60 and selects the input thatrepresents the result of comparison of the trigger code to the contentof the memory location that is being updated. Thus, if the memorylocation that is being updated corresponds to a pixel inside the triggerregion, multiplexer 86 provides a logical one at its output andotherwise provides a logical zero at its output. The output ofmultiplexer 86 is applied to processor 18, which may respond to alogical one received from multiplexer 86 by issuing a trigger toacquisition circuit 54 to initiate termination of the acquisition.

The look-up table stored in RAM 74 is loaded into the look-up RAM bymain processor 18. In order to prevent issue of spurious triggers, thelook-up table is such that no location that contains the trigger codewill be changed. For example, if the trigger code is decimal 2, thelook-up table may be such that RAM 74 returns the values indicated inthe right column of Table I in response to the input values indicated inthe left column of Table I.

                  TABLE I                                                         ______________________________________                                                Address                                                                              Data                                                           ______________________________________                                                0      1                                                                      1      3                                                                      2      2                                                                      3      4                                                                      4      5                                                                      .      .                                                                      .      .                                                                      .      .                                                                      14     15                                                                     15     15                                                             ______________________________________                                    

Pixel manipulator 70 also comprises a decrementer, which enablesoscilloscope 2 to emulate the persistence mode of operation of an analogoscilloscope. When emulating the persistence mode, oscilloscope 2 fromtime to time executes a decay cycle in response to a signal provided bya decay cycle initiator 96. During a decay step, memory addressgenerator 60 generates a memory address vector internally and thecontents of the four memory locations identified by that memory addressvector are applied through latch 72 to the decrementer. In the case ofthe illustrated embodiment of the invention, the decrementer comprises asecond look-up RAM 80, whose data lines are connected to the secondinput of multiplexer 78. Look-up RAM 80 returns four output values,related to the input values respectively by the look-up table stored inRAM 80, and these modified values are placed on the data bus bymultiplexer 78 and are written back into the appropriate memorylocations of memory 36. After each read, modify, write cycle, memoryaddress generator 60 generates a new memory address vector. In order toreduce intensity pumping effects, the memory address vectors generatedin successive decay steps point to locations that are staggered over theaddress space of memory 36. In a decay cycle, which constitutes asuccession of decay steps, all memory locations containing non-zerovalues are decremented.

In a decay cycle, the contents of the memory locations corresponding topixels outside the trigger region are decremented, so that the pixelsprogressively fade unless the corresponding memory locations areincremented, in acquisition cycles, at least as rapidly as they aredecremented in decay cycles.

In a decay cycle, it is not necessary to test the numbers loaded intolatch 72 to determine whether a memory location containing the triggercode has been addressed, but it is necessary to ensure that locationsthat have been loaded with the trigger code are not modified. If thetrigger code is decimal 2, this may be accomplished by loading decay RAM80 with a table such that it provides as output the value indicated inthe right column of Table II in response to the input indicated in theleft column of Table II.

                  TABLE II                                                        ______________________________________                                                Address                                                                              Data                                                           ______________________________________                                                0      0                                                                      1      0                                                                      2      2                                                                      3      1                                                                      4      3                                                                      .      .                                                                      .      .                                                                      .      .                                                                      14     13                                                                     15     14                                                             ______________________________________                                    

The value of decimal 2 for the trigger code is chosen because it issufficient to enable the trigger region to be easily discerned by theoperator of the oscilloscope.

It will be appreciated that the invention is not restricted to theparticular embodiment that has been described, and that variations maybe made therein without departing from the scope of the invention asdefined in the appended claims and equivalents thereof. For example, itis not essential to use two separate look-up RAMs for the pixel updatecycle and the decay cycle, since the update table and the decay tablemay be loaded into a single RAM in alternating fashion. However, use oftwo separate RAMs frees the system from timing and other constraints,imposed by using a single look-up RAM for the two functions. Further, itis not necessary to employ look-up tables for the update and decayoperations, since these operations may be performed by use of arithmeticlogic units functioning as adders and subtractors respectively, providedthat steps are taken to avoid altering the input values that are equalto the trigger code. This may be accomplished on the update side by alook-up RAM loaded with a table that returns the same output value for agiven input value except in the case where the input value, provided bythe adder, corresponds to the value that is returned by the adder inresponse to the trigger code, in which case the table returns thetrigger code. A similar expedient may be employed on the decay side. Anadvantage of using an arithmetic logic unit for updating is that itfacilitates the display of intensified zones, as described in abandonedpatent application Ser. No. 07/563,774 filed Aug. 6, 1990 and use of anarithmetic logic unit for decay facilitates adaptive operation of thedecay function, as described in co-pending patent application Ser. No.07/563,656 filed Aug. 6, 1990. It is not essential that the number ofmemory locations be equal to the number of displayable pixels, so longas there are at least as many memory locations as displayable pixels.

Further information regarding functions that can be performed using thesame general architecture shown in the drawing is contained in patentapplication Ser. No. 07/149,792 filed Jan. 29, 1988 and in abandonedpatent application Ser. No. 07/445,138 filed Dec. 4, 1989. Thedisclosure of all four applications mentioned above is herebyincorporated by reference herein.

I claim:
 1. A method of operating a buffer memory to generate a triggerwhen a waveform in the form of pairs of data words falls outside adefined region, the buffer memory having an array of memory locationsdefined by first and second address words, each memory location storinga numerical value, said method comprising the steps of:(a) loadingselected memory locations of the buffer memory corresponding to thedefined region with a trigger code, (b) receiving a first data word anda second data word from each pair of data words, (c) reading from thebuffer memory the numerical value stored at the memory location whosefirst and second address words are defined by the first and second datawords, and (d) generating the trigger when the numerical value read instep (c) bears a predetermined relationship to said trigger code.
 2. Themethod according to claim 1 further comprising the steps of:incrementingthe numerical value read in step (c) by a selected amount when thenumerical value does not bear said predetermined relationship to saidtrigger code, and writing the incremented numerical value back to thememory location that was read in step (c).
 3. The method according toclaim 1 further comprising the steps of:(e) reading the numerical valuefrom each memory location of the buffer memory, (f) decrementing eachnumerical value that does not bear the predetermined relationship to thetrigger code by a selected amount, and (g) writing the decrementednumerical values back to the respective memory locations.
 4. The methodaccording to claim 1 wherein the buffer memory has at least twocoextensive arrays of memory locations, the locations of each arraybeing defined by the first and second address words, and step (b)comprises the steps of:(b)(i) acquiring the first and second data wordsfrom an input signal, and (b)(ii) employing the first data word and theupper m bits of the second data word to determine the first and secondaddress words to select a memory location in each of said coextensivearrays, step (c) comprises the step of reading the numerical values fromthe selected memory location in each array, and step (d) comprises thesteps of:(d)(i) comparing the numerical values from the selected memorylocations with the trigger code, and (d)(ii) employing the lower p bitsof the second data word to select one of the results of the comparingstep to determine whether said trigger should be generated.
 5. A methodof operating a buffer memory that has a multiplicity of memory locationsin an address space having a first dimension and a second dimension,each memory location storing a numerical value, said method comprisingthe steps of:(a) loading the memory locations within a selected area ofthe address space with a trigger code, (b) acquiring a succession ofpairs of data words from an input signal, each pair being composed of afirst data word and a second data word, the range of the first data wordbeing equal to at least the range of the first dimension of the addressspace and the range of the second data word being equal to at least therange of the second dimension of the address space, (c) for each pair ofdata words,(i) reading from the buffer memory the numerical value storedat the memory location whose address in the first dimension of theaddress space is defined by a first address word and whose address inthe second dimension of the address space is defined by a second addressword, the first and second address words being related in apredetermined fashion to the first and second data words, (ii) comparingsaid numerical value with said trigger code, (iii) generating apredetermined response signal when said numerical value bears apredetermined relationship to said trigger code, and (iv) incrementingsaid numerical value by a predetermined amount and writing theincremented numerical value to the memory location that was read in step(c)(i) when said numerical value does not bear the predeterminedrelationship to said trigger code, (d) subsequently generating the firstand second address words independently of the first and second datawords, and (e) for the first and second address words(i) reading fromthe buffer memory the numerical value stored at the memory locationdefined by the first and second address words, (ii) writing thenumerical value unchanged back to the memory location read in step(e)(i) when said numerical value bears the predetermined relationship tosaid trigger code, and (iii) decrementing the numerical value by aselected amount and writing the decremented numerical value back to thememory location read in step (e)(i) when said numerical value does notbear the predetermined relationship to said trigger code.
 6. The methodaccording to claim 5 further comprising before step (a) the step ofdefining said selected area of the address space.
 7. Buffer memoryapparatus for generating a trigger when a waveform in the form of pairsof data words falls outside a defined region comprising:a multiplicityof memory locations occupying a two-dimensional address space and eachstoring a numerical value, means for defining an area of the addressspace corresponding to the defined region and loading the memorylocations within the defined area each with a trigger code, means forreceiving the pairs of data words, each pair having a first data wordand a second data word, means responsive to each pair of data words fromthe receiving means for reading from the buffer memory the numericalvalue stored at the memory location whose address is defined by a firstaddress word and a second address word related in a predeterminedfashion to the first and second data words, comparing the numericalvalue read from the buffer memory with said trigger code, and generatingthe trigger when said numerical value bears a predetermined relationshipto said trigger code.